Currently, integrated circuit (IC) package assemblies may include a solder mask layer composed of polymer as an outermost layer of a package substrate to facilitate formation of second-level or “package-level” interconnects. However, present polymer-based solder mask layers may be associated with higher loss and/or cross-talk resulting in lower power efficiency for electrical signals routed through the second-level interconnects. Cleaning of build-up layers of the package substrate may be difficult in current processes that utilize a polymer-based solder mask layer. Additionally, forming openings in the polymer-based solder mask layer may be costly.
Emerging IC package assemblies may further include a bridge configured to route electrical signals between dies mounted on the IC package assembly. Current techniques to align and/or couple the bridge with the IC package assembly may be costly or may not be capable of fabricating fine line and space and provide high input/output (I/O) count between dies or may be otherwise challenging owing to constraints in temporary position alignment technology and/or differences in coefficient of thermal expansion (CTE) between the bridge and other materials of the IC package assembly.